The invention relates to making temporary, pressure connections between electronic components and, more particularly, to techniques for performing test and burn-in procedures on semiconductor devices prior to their packaging, preferably prior to the individual semiconductor devices being singulated from a semiconductor wafer.
Techniques of making pressure connections with composite interconnection elements (resilient contact structures) have been discussed in commonly-owned, copending U.S. patent application Ser. No. 08/452,255 filed May 26, 1995 (xe2x80x9cPARENT CASExe2x80x9d).
As discussed in commonly-owned, copending U.S. Pat. No. 5,974,662, issued Nov. 2,1999, individual semiconductor (integrated circuit) devices (dies) are typically produced by creating several identical devices on a semiconductor wafer, using known techniques of photolithography, deposition, and the like. Generally, these processes are intended to create a plurality of fully-functional integrated circuit devices, prior to singulating (severing) the individual dies from the semiconductor wafer. In practice, however, certain physical defects in the wafer itself and certain defects in the processing of the wafer inevitably lead to some of the dies being xe2x80x9cgoodxe2x80x9d (fully-functional) and some of the dies being xe2x80x9cbadxe2x80x9d (non-functional).
It is generally desirable to be able to identify which of the plurality of dies on a wafer are good dies prior to their packaging, and preferably prior to their being singulated from the wafer. To this end, a wafer xe2x80x9ctesterxe2x80x9d or xe2x80x9cproberxe2x80x9d may advantageously be employed to make a plurality of discrete pressure connections to a like plurality of discrete connection pads (bond pads) on the dies. In this manner, the semiconductor dies can be tested and exercised, prior to singulating the dies from the wafer.
A conventional component of a wafer tester is a xe2x80x9cprobe cardxe2x80x9d to which a plurality of probe elements are connectedxe2x80x94tips of the probe elements effecting the pressure connections to the respective bond pads of the semiconductor dies.
Certain difficulties are inherent in any technique for probing semiconductor dies. For example, modern integrated circuits include many thousands of transistor elements requiring many hundreds of bond pads disposed in close proximity to one another (e.g., 5 mils center-to-center). Moreover, the layout of the bond pads need not be limited to single rows of bond pads disposed close to the peripheral edges of the die (See, e.g., U.S. Pat. No. 5,453,583).
To effect reliable pressure connections between the probe elements and the semiconductor die one must be concerned with several parameters including, but not limited to: alignment, probe force, overdrive, contact force, balanced contact force, scrub, contact resistance, and planarization. A general discussion of these parameters may be found in U.S. Pat. No. 4,837,622, entitled HIGH DENSITY PROBE CARD, incorporated by reference herein, which discloses a high density epoxy ring probe card including a unitary printed circuit board having a central opening adapted to receive a preformed epoxy ring array of probe elements.
Generally, prior art probe card assemblies include a plurality of tungsten needles (probe elements) extending as cantilevers from a surface of a probe card. The tungsten needles may be mounted in any suitable manner to the probe card, such as by the intermediary of an epoxy ring, as discussed hereinabove. Generally, in any case, the needles are wired to terminals of the probe card through the intermediary of a separate and distinct wire connecting the needles to the terminals of the probe card.
Probe cards are typically formed as circular rings, with hundreds of probe elements (needles) extending from an inner periphery of the ring (and wired to terminals of the probe card) Circuit modules, and conductive traces (lines) of preferably equal length, are associated with each of the probe elements. This ring-shape layout makes it difficult, and in some cases impossible, to probe a plurality of unsingulated semiconductor dies (multiple sites) on a wafer, especially when the bond pads of each semiconductor die are arranged in other than two linear arrays along two opposite edges of the semiconductor die.
Wafer testers may alternately employ a probe membrane having a central contact bump (probe element) area, as is discussed in U.S. Pat. No. 5,422,574, entitled LARGE SCALE PROTRUSION MEMBRANE FOR SEMICONDUCTOR DEVICES UNDER TEST WITH VERY HIGH PIN COUNTS, incorporated by reference herein. As noted in this patent, xe2x80x9cA test system typically comprises a test controller for executing and controlling a series of test programs, a wafer dispensing system for mechanically handling and positioning wafers in preparation for testing and a probe card for maintaining an accurate mechanical contact with the device-under-test (DUT).xe2x80x9d (column 1, lines 41-46).
Additional references, incorporated by reference herein, as indicative of the state of the art in testing semiconductor devices, include U.S. Pat. No. 5,442,282 (TESTING AND EXERCISING INDIVIDUAL UNSINGULATED DIES ON A WAFER); U.S. Pat. No. 5,382,898 (HIGH DENSITY PROBE CARD FOR TESTING ELECTRICAL CIRCUITS); U.S. Pat. No. 5,378,982 TEST PROBE FOR PANEL HAVING AN OVERLYING PROTECTIVE MEMBER ADJACENT PANEL CONTACTS); U.S. Pat. No. 5,339,027 (RIGID-FLEX CIRCUITS WITH RAISED FEATURES AS IC TEST PROBES); U.S. Pat. No. 5,180,977 (MEMBRANE PROBE CONTACT BUMP COMPLIANCY SYSTEM); U.S. Pat. No. 5,066,907 (PROBE SYSTEM FOR DEVICE AND CIRCUIT TESTING); U.S. Pat. No. 4,757,256 (HIGH DENSITY PROBE CARD); U.S. Pat. No. 4,161,692 (PROBE DEVICE FOR INTEGRATED CIRCUIT WAFERS); and U.S. Pat. No. 3,990,689 (ADJUSTABLE HOLDER ASSEMBLY FOR POSITIONING A VACUUM CHUCK).
Generally, interconnections between electronic components can be classified into the two broad categories of xe2x80x9crelatively permanentxe2x80x9d and xe2x80x9creadily demountablexe2x80x9d.
An example of a xe2x80x9crelatively permanentxe2x80x9d connection is a solder joint. Once two components are soldered to one another, a process of unsoldering must be used to separate the components. A wire bond is another example of a xe2x80x9crelatively permanentxe2x80x9d connection.
An example of a xe2x80x9creadily demountablexe2x80x9d connection is rigid pins of one electronic component being received by resilient socket elements of another electronic component. The socket elements exert a contact force (pressure) on the pins in an amount sufficient to ensure a reliable electrical connection therebetween.
Interconnection elements intended to make pressure contact with terminals of an electronic component are referred to herein as xe2x80x9cspringsxe2x80x9d or xe2x80x9cspring elementsxe2x80x9d. Generally, a certain minimum contact force is desired to effect reliable pressure contact to electronic components (e.g., to terminals on electronic components). For example, a contact (load) force of approximately 15 grams (including as little as 2 grams or less and as much as 150 grams or more, per contact) may be desired to ensure that a reliable electrical connection is made to a terminal of an electronic component which may be contaminated with films on its surface, or which has corrosion or oxidation products on its surface. The minimum contact force required of each spring demands either that the yield strength of the spring material or that the size of the spring element are increased. As a general proposition, the higher the yield strength of a material, the more difficult it will be to work with (e.g., punch, bend, etc.). And the desire to make springs smaller essentially rules out making them larger in cross-section.
Probe elements (other than contact bumps of membrane probes) are a class of spring elements of particular relevance to the present invention. Prior art probe elements are commonly fabricated from tungsten, a relatively hard (high yield strength) material. When it is desired to mount such relatively hard materials to terminals of an electronic component, relatively xe2x80x9chostilexe2x80x9d (e.g., high temperature) processes such as brazing are required. Such xe2x80x9chostilexe2x80x9d processes are generally not desirable (and often not feasible) in the context of certain relatively xe2x80x9cfragilexe2x80x9d electronic components such as semiconductor devices. In contrast thereto, wire bonding is an example of a relatively xe2x80x9cfriendlyxe2x80x9d processes which is much less potentially damaging to fragile electronic components than brazing. Soldering is another example of a relatively xe2x80x9cfriendlyxe2x80x9d process. However, both solder and gold are relatively soft (low yield strength) materials which will not function well as spring elements.
A subtle problem associated with interconnection elements, including spring contacts, is that, often, the terminals of an electronic component are not perfectly coplanar. Interconnection elements lacking in some mechanism incorporated therewith for accommodating these xe2x80x9ctolerancesxe2x80x9d (gross non-planarities) will be hard pressed to make consistent contact pressure contact with the terminals of the electronic component.
The following U.S. Patents, incorporated by reference herein, are cited as being of general interest vis-a-vis making connections, particularly pressure connections, to electronic components: U.S. Pat. No. 5,386,344 (FLEX CIRCUIT. CARD ELASTOMERIC CABLE CONNECTOR ASSEMBLY); U.S. Pat. No. 5,336,380 (SPRING BIASED TAPERED CONTACT ELEMENTS FOR ELECTRICAL CONNECTORS AND INTEGRATED CIRCUIT PACKAGES); U.S. Pat. No. 5,317,479 (PLATED COMPLIANT LEAD); U.S. Pat. No. 5,086,337 (CONNECTING STRUCTURE OF ELECTRONIC PART AND ELECTRONIC DEVICE USING THE STRUCTURE); U.S. Pat. No. 5,067,007 (SEMICONDUCTOR DEVICE. HAVING LEADS FOR MOUNTING TO A SURFACE OF A PRINTED CIRCUIT BOARD); U.S. Pat. No. 4,989,069 (SEMICONDUCTOR PACKAGE HAVING LEADS THAT BREAK-AWAY FROM SUPPORTS); U.S. Pat. No. 4,893,172 (CONNECTING STRUCTURE FOR ELECTRONIC PART AND METHOD OF MANUFACTURING THE SAME); U.S. Pat. No. 4,793,814 (ELECTRICAL CIRCUIT BOARD INTERCONNECT); U.S. Pat. No. 4,777,564 (LEADFORM FOR USE WITH SURFACE MOUNTED COMPONENTS); U.S. Pat. No. 4,764,848 (SURFACE MOUNTED ARRAY STRAIN RELIEF DEVICE); U.S. Pat. No. 4,667,219 (SEMICONDUCTOR CHIP INTERFACE); U.S. Pat. No. 4,642,889 (COMPLIANT INTERCONNECTION AND METHOD THEREFOR); U.S. Pat. No. 4,330,165 (PRESS-CONTACT TYPE INTERCONNECTORS); U.S. Pat. No. 4,295,700 (INTERCONNECTORS); U.S. Pat. No. 4,067,104 (METHOD OF FABRICATING AN ARRAY OF FLEXIBLE METALLIC INTERCONNECTS FOR COUPLING MICROELECTRONICS COMPONENTS); U.S. Pat. No. 3,795,037 (ELECTRICAL CONNECTOR DEVICES); U.S. Pat. No. 3,616,532 (MULTILAYER PRINTED CIRCUIT, ELECTRICAL INTERCONNECTION DEVICE); and U.S. Pat. No. 3,509,270 (INTERCONNECTION FOR PRINTED CIRCUITS AND METHOD OF MAKING SAME).
In-the aforementioned PARENT CASE, techniques are disclosed for fabricating composite interconnection elements (resilient contact structures, spring elements) directly upon electronic components. In cases where a large number of such spring elements are required, failure to yield (successfully manufacture) but one of the great many spring elements may result in an entire component being defective (unusable or, at best, requiring extensive rework).
Moreover, in instances wherein it is desired to fabricate a great many spring contacts over a large surface area, for example to provide for full semiconductor wafer testing in one pass, it is difficult to find an appropriate (e.g., matched coefficient of thermal expansion) substrate to which the great many spring contacts can successfully be mounted.
It is an object of the invention to provide an improved technique of mounting a large plurality of probe elements on an electronic component, such as a probe card, covering a large area and avoiding problems associated with yielding (successfully fabricating) the probe elements, particularly probe elements which are spring elements, directly on the electronic component.
It is an object of the present invention to provide a technique for providing electronic components, such as space transformer substrates and semiconductor devices with spring contacts, while avoiding problems (e.g., yield) associated with fabricating the spring contacts directly upon the electronic components.
According to the invention, probe elements such as spring contacts are pre-fabricated on individual spring contact carriers (xe2x80x9ctilesxe2x80x9d). A number of these tiles are mounted to another component (such as a space transformer substrate or a printed circuit board) in a defined relationship with one another, preferably so that the tips of the spring contacts are coplanar with one another. The tile substrates are preferably relatively inexpensive, and conducive to successfully yielding spring contacts. Terminals on an opposite surface of the tile are joined to terminals of an electronic-component such as a space transformer substrate, or one or more semiconductor devices (including unsingulated semiconductor devices) by solder, z-axis conducting adhesive, or the like.
The spring contacts are preferably composite interconnection elements. However, any suitable spring contact may be tiled in the manner of the invention, such as monolithic spring contacts and membrane probe sections.
As used herein, the term xe2x80x9cprobe elementxe2x80x9d includes any element such as a composite interconnection element, spring contact, spring element, contact bump, or the like, suited to effect a pressure connection to terminals (e.g., bond pads) of an electronic component (e.g., a semiconductor die, including unsingulated semiconductor dies resident on a semiconductor wafer).
As used herein, the term xe2x80x9ctilexe2x80x9d includes any component having probe elements on a surface thereof, a plurality (preferably identical) of which can be mounted to a larger substrate, thereby avoiding fabricating said probe elements directly upon the larger substrate.
As used herein, the term xe2x80x9ctile substratexe2x80x9d includes a solid substrate (e.g., 602, 902, 922,942, 962) as well as a frame (e.g., 1002, 1002a, 1002b, 1002c), or the like.
As used herein, the term xe2x80x9ca larger substratexe2x80x9d is any substrate to which a plurality of tiles can be mounted, to the surface thereof. Generally, at least four tiles would be mounted to the larger substrate, dictating that the surface area of larger substrate would be at least four times as great as the surface area of an individual tile. This specifically includes the xe2x80x9cspace transformerxe2x80x9d of a probe card assembly.
As may be used herein, a xe2x80x9csparkxe2x80x9d is an electrical discharge.
According to an embodiment of the invention, a plurality of such tiles can be attached and connected to a single space transformer component of a probe card assembly to effect wafer-level (multiple site) testing, wherein an entire semiconductor wafer can be burned-in and/or tested in by making simultaneous pressure connections between the plurality of probe elements and a plurality of bond pads. (terminals) of the semiconductor devices which are resident on the semiconductor wafer.
According to a feature of the invention, the tiles can be single layer substrates, or can be multilayer substrates effecting a degree of space-transformation.
According to a feature of the invention, a plurality of tiles having spring contact elements fabricated on a surface thereof can be fabricated from a single, inexpensive substrate such as a ceramic wafer, which is subsequently diced to result in a plurality of separate, preferably identical tiles which can be individually mounted to the surface of a space transformer or to the surface of a semiconductor wafer, or other electronic component).
According to an aspect of the invention, in order to enhance self-alignment of one or more tiles to the corresponding surface of the electronic component to which they are mounted, the electronic component and the tile(s) are each provided with at least one solderable feature that, with solder disposed therebetween and during reflow heating, will provide enhanced momentum for effecting self-alignment of the tile substrate to the electronic component.
An advantage of the present invention is that tiles may be mounted directly to semiconductor devices, including fully-populated C4 dies with active devices, either prior to or after their singulation from a semiconductor wafer. In this manner, spring contact elements are readily mounted to semiconductor devices, while avoiding fabricating the spring contact elements, directly upon the semiconductor devices.
An advantage of the present invention is that the tiles upon which the spring elements are fabricated can be an existing xe2x80x9cC4xe2x80x9d package having solder bumps on a surface opposite the spring elements. In this manner, the tiles can be mounted to the surface of an electronic component (e.g., space transformer, semiconductor wafer, or the like) by reflow heating.
An advantage to the technique of using tiles, rather than fabricating spring elements directly upon the surface of the electronic component is that the electronic component is readily re-worked, simply by replacing selected ones of the one or more tiles attached/connected thereto.
The present invention is applicable to using tiles to populate larger substrates, and the probe elements on the tiles may also be contact bumps of the type found in membrane probes.
According to a feature of the invention, semiconductor devices which have had spring contact elements mounted thereto in the aforementioned manner are readily tested and/or burned-in using a simple test fixture which may be as simple as a printed circuit board (PCB) having terminals (pads) arranged to mate (by pressure contact) with the tips of the spring contact elements.
The space transformer substrate with tiles mounted thereto is suitably employed as a component of a probe card assembly which includes a probe card (electronic component) having a top surface, a bottom surface and a plurality of terminals on the top surface thereof; an interposer (electronic component) having a top surface, a bottom surface, a first plurality of resilient contact structures extending from terminals on the bottom surface thereof and a second plurality of contact structures extending from terminals on the top surface thereof. The interposer is situated between the probe card and the space transformer, as described in commonly-owned, copending U.S. Pat. No. 5,974,662 issued Nov. 2, 1999.
The use of the term xe2x80x9ccompositexe2x80x9d, throughout the description set forth herein, is consistent with a xe2x80x98genericxe2x80x99 meaning of the term (e.g., formed of two or more elements), and is not to be confused with any usage of the term xe2x80x9ccompositexe2x80x9d in other fields of endeavor, for example, as it may be applied to materials such as glass, carbon or other fibers supported in a matrix of resin or the like.
As used herein, the term xe2x80x9cspring shapexe2x80x9d refers to virtually any shape of an elongate element which will exhibit elastic (restorative) movement of an end (tip) of the elongate element with respect to a force applied to the tip. This includes elongate elements shaped to have one or more bends, as well as substantially straight elongate elements.
As used herein, the terms xe2x80x9ccontact areaxe2x80x9d, xe2x80x9cterminalxe2x80x9d, xe2x80x9cpadxe2x80x9d, and the like refer to any conductive area on any electronic component to which an interconnection element is mounted or makes contact.
Alternatively, the core is shaped prior to mounting to an electronic component.
Alternatively, the core is mounted to or is a part of a sacrificial substrate which is not an electronic component. The sacrificial substrate is removed after shaping, and either before or after overcoating. According to an aspect of the invention, tips having various topographies can be disposed at the contact ends of the interconnection elements. (See also FIGS. 11A-11F of the PARENT CASE.)
In an embodiment of the invention, the core is a xe2x80x9csoftxe2x80x9d material having a relatively low yield strength, and is overcoated with a xe2x80x9chardxe2x80x9d material having a relatively high yield strength. For example, a soft material such as a gold wire is attached (e.g., by wire bonding) to a bond pad of a semiconductor device and is overcoated (e.g., by electrochemical plating) with a hard material such nickel and its alloys.
Vis-a-vis overcoating the core, single and multi-layer overcoatings, xe2x80x9croughxe2x80x9d overcoatings having microprotrusions (see also FIGS. 5C and 5D of the PARENT CASE), and overcoatings extending the entire length of or only a portion of the length of the core, are described. In the latter case, the tip of the core may suitably be exposed for making contact to an electronic component (see also FIG. 5B of the PARENT CASE).
Generally, throughout the description set forth herein, the term xe2x80x9cplatingxe2x80x9d is used as exemplary of a number of techniques for overcoating the core. It is within the scope of this invention that the core can be overcoated by any suitable technique including, but not limited to: various processes involving deposition of materials out of aqueous solutions; electrolytic plating; electroless plating; chemical vapor deposition (CVD); physical vapor deposition (PVD); processes causing the deposition of materials through induced disintegration of liquid or solid precursors; and the like, all of these techniques for depositing materials being generally well known.
Generally, for overcoating the core with a metallic material such as nickel, electrochemical processes are preferred, especially electrolytic plating.
In another embodiment of the invention, the core is an elongate element of a xe2x80x9chardxe2x80x9d material, inherently suitable to functioning as a spring element, and is mounted at one end to a terminal of an electronic component. The core, and at least an adjacent area of the terminal, is overcoated with a material which will enhance anchoring the core to the terminal. In this manner, it is not necessary that the core be well-mounted to the terminal prior to overcoating, and processes which are less potentially damaging to the electronic component may be employed to xe2x80x9ctackxe2x80x9d the core in place for subsequent overcoating. These xe2x80x9cfriendlyxe2x80x9d processes include soldering, gluing, and piercing an end of the hard core into a soft portion of the terminal.
Preferably, the core is in the form of a wire. Alternatively, the core is a flat tab (conductive metallic ribbon).
Representative materials, both for the core and for the overcoatings, are disclosed.
In the main hereinafter, techniques involving beginning with a relatively soft (low yield strength) core, which is generally of very small dimension (e.g., 3.0 mil or less) are described. Soft materials, such as gold, which attach easily to the metallization (e.g., aluminum) of semiconductor devices, generally lack sufficient resiliency to function as springs. (Such soft, metallic materials exhibit primarily plastic, rather than elastic deformation.) Other soft materials which may attach easily to semiconductor devices and possess appropriate resiliency are often electrically non-conductive, as in the case of most elastomeric materials. In either case, desired structural and electrical characteristics can be imparted to the resulting composite interconnection element by the overcoating applied over the core. The resulting composite interconnection element can be made very small, yet can exhibit appropriate contact forces. Moreover, a plurality of such composite interconnection elements can be arranged at a fine pitch (e.g., 10 mils), even though they have a length (e.g., 100 mils) which is much greater than the distance to a neighboring composite interconnection element (the distance between neighboring interconnection elements being termed xe2x80x9cpitchxe2x80x9d).
It is within the scope of this invention that composite interconnection elements can be fabricated on a microminiature scale, for example as xe2x80x9cmicrospringsxe2x80x9d for connectors and sockets, having cross-sectional dimensions on the order of twenty-five microns (xcexcm), or less. This ability to manufacture reliable interconnection having dimensions measured in microns, rather than mils, squarely addresses the evolving needs of existing interconnection technology and future area array technology.
The composite interconnection elements of the invention exhibit superior electrical characteristics, including electrical conductivity, solderability and low contact resistance. In many cases, deflection of the interconnection element in response to applied contact forces results in a xe2x80x9cwipingxe2x80x9d contact, which helps ensure that a reliable contact is made.
An additional advantage of the present invention is that connections made with the interconnection elements of the present invention are readily demountable. Soldering, to effect the interconnection to a terminal of an electronic component is optional, but is generally not preferred at a system level.
According to an aspect of the invention, techniques are described for making interconnection elements having controlled impedance. These techniques generally involve coating (e.g., electrophoretically) a conductive core or an entire composite interconnection element with a dielectric material (insulating layer), and overcoating the dielectric material with an outer layer of a conductive material. By grounding the outer conductive material layer, the resulting interconnection element can effectively be shielded, and its impedance can readily be controlled. (See also FIG. 10K of the PARENT CASE.) According to an aspect of the invention, interconnection elements can be pre-fabricated as individual units, for later attachment to electronic components. Various techniques for accomplishing this objective are set forth herein. Although not specifically covered in this document, it is deemed to be relatively straightforward to fabricate a machine that will handle the mounting of a plurality of individual interconnection elements to a substrate or, alternatively, suspending a plurality of individual interconnection elements in an elastomer, or on a support substrate.
It should clearly be understood that the composite interconnection element of the present invention differs dramatically from interconnection elements of the prior art which have been coated to enhance their electrical conductivity characteristics or to enhance their resistance to corrosion.
The overcoating of the present invention is specifically intended to substantially enhance anchoring of the interconnection element to a terminal of an electronic component and/or to impart desired resilient characteristics to the resulting composite interconnection element. Stresses (contact forces) are directed to portions of the interconnection elements which are specifically intended to absorb the stresses.
It should also be appreciated that the present invention provides essentially a new technique for making spring structures. Generally, the operative structure of the resulting spring is a product of plating, rather than of bending and shaping. This opens the door to using a wide variety of materials to establish the spring shape, and a variety of xe2x80x9cfriendlyxe2x80x9d processes for attaching the xe2x80x9cfalseworkxe2x80x9d of the core to electronic components. The overcoating functions as a xe2x80x9csuperstructurexe2x80x9d, over the xe2x80x9cfalseworkxe2x80x9d of the core, both of which terms have their origins in the field of civil engineering.
According to an aspect of the invention, any of the resilient contact structures may be formed as at least two composite interconnection elements.
A particularly useful application for the present invention is to provide a method of probing (electrically contacting) a testable area of an electronic component with a plurality of spring contact elements, by populating (mounting and connecting) a plurality of contact carriers (tile substrates) to a larger substrate and urging the large substrate and the electronic component towards on another so that spring contact elements extending from a surface of the tile substrates make contact with corresponding terminals on the testable area of the electronic component. The electronic component may be a semiconductor water, in which case the testable area would be a plurality of die sites on the semiconductor wafer. The ability of all of the spring contacts to make contact with a plurality of die sites, all at once, can facilitate such processes as wafer-level burn-in. However, it is not necessary that the entire electronic component be contacted at once. Advantages will accrue when a substantial portion, such as at least half, of the electronic component is contacted at once. The electronic component may also, for example, be a printed circuit board (PCB) or a liquid crystal display (LCD) panel.